Snapsolve any problem by taking a picture.
Try it in the Numerade app?
a) How would you extend the single-cycle datapath in the figure below to implement the CBNZ (Branch on not zero) Instruction? Similar to CBZ except that the branch is taken when the register is not zero. Explain your work. b) The processor needs to compute the next PC after each instruction. Write a Verilog module which computes the next PC. Be sure to include the B and CBZ cases. You may use the output of the "Control" module as shown in the figure in the previous problem. c) How would you extend the single-cycle data and control paths in the figure above to implement the BR (Branch to Register) Instruction? d) Investigate the possibility of adding a new instruction SRBR that combines two existing instructions. For example, SRBR X30, SP, 16 will implement: ADD SP, SP, 16 BR X30 List any additional control or datapaths that need to be added above what is needed for BR. What will be the values of Reg2Loc, UncondBR, Branch, MemToReg, RegWrite, MemRead, MemWrite, ALUSrc, and any control signals you added in the previous problem and added for this problem. Ado u X ALU Add result Reg2Loc Uncondbranch Branch MemRead Instruction [31-21] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Shift left 2 Instruction[9-5] Read address Read register 1 Read data 1 Read register 2 Write Read register data 2 PC Instruction[20-16] M u X Zero ALU ALU result Instruction [31-0] Instruction memory Read Address data Instruction [4-0] M Write data Registers X Data Write memory data Instruction[31-0] 32 Sign-extend ALU control Instruction[31-21]
Submitted by Thomas S. Feb. 11, 2023 04:28 p.m.
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